1. Field of the Invention
This invention relates generally to the electronic circuits and, more particularly, to circuits that can be used as an input stage for an operational amplifier. The input stage to which present invention has application includes components coupled in series to increase the voltage rating of the stage. A feedback circuit and method are described which eliminates error currents in the differential stage, currents which would adversely affect the drift and the offset voltages as the power supply or the common mode voltage changes after the input stage has been calibrated for the initial conditions.
2. Description of the Related Art
Referring now to FIG. 1, an input stage, according to the prior art, having components coupled in series in a cascode configuration. The negative terminal of a power supply T1, which is shown coupled to the ground potential, is coupled to a first terminal of resistor R11 and to a first terminal of resistor R13. The second terminal of resistor R11 is coupled to a gate terminal of an enhancement mode MOSFET transistor Q12 and to a first terminal of resistor R12. The second terminal of resistor R12 is coupled to a first terminal of resistor R14 and to a drain terminal of transistor Q12. A second terminal of resistor R13 is coupled to a source terminal of an enhancement mode MOSFET transistor Q13. A drain terminal of transistor Q13 is coupled to a source terminal of transistor Q12. A second terminal of resistor R14 is coupled to a positive terminal T2 of a power supply. The SIGNAL IN for the stag is applied between the common terminal and a gate terminal of transistor Q13. The SIGNAL OUT V.sub.0 is supplied between ground potential and the first terminal of resistor R14.
The circuit shown in FIG. 1 includes two (transistor) components, Q12 and Q13, coupled in series. However, any number of (transistor) components can be coupled in series using similar techniques. In addition, the common terminal, shown as being coupled to the ground potential, can be decoupled from the ground potential and be permitted to float electrically. The resistors R11 and R12 provide biasing for the transistors with the result that approximately one half of the supply voltage is applied across each resistor.
When an input signal applied to the input stage is changed, the voltage across transistors Q12 and Q13 will vary. The variation in the voltage across the two transistors Q12 and Q13 will result in variation in the current through resistors R11 and R12. The total stage current changes thereby and is dependent of the SIGNAL IN.
Referring next to FIG. 2, a simplified circuit diagram of a operational amplifier input stage wherein protection of the differential amplifier from excessive voltage is required. A negative voltage terminal T1 of a voltage supply is coupled to a first terminal of resistor 27, and a first terminal of resistor R26 and a negative terminal of V21. A second terminal of resistor R27 is coupled to source terminal of an enhanced mode metal oxide semiconductor field effect (MOSFET) transistor Q20. The positive terminal of power supply V21 is coupled to a gate of transistor Q20. A drain terminal of transistor Q20 is coupled to the source of enhanced mode MOSFET transistor Q29. A second terminal of resistor R26 is coupled to a first terminal of resistor R25 and a gate terminal of transistor Q29. A second terminal of resistor R25 is coupled to a source terminal of field effect (FET) transistor Q27, a drain terminal of transistor Q29, a first terminal of resistor R28, and a source terminal of FET transistor Q28. A drain terminal of transistor Q27 is coupled to a first terminal of resistor R22 and to a source terminal of enhanced mode MOSFET transistor Q24. A drain terminal of transistor Q28 is coupled to a source terminal of enhanced mode MOSFET transistor Q26 and to a first terminal of resistor R24. A second terminal of resistor R28 is coupled to a gate terminal of transistor Q24, a gate terminal of transistor Q26 and a first terminal of current source I22. A second terminal of resistor R22 is coupled to a gate terminal of enhanced mode MOSFET transistor Q23 and to a first terminal of resistor R21. A drain terminal of transistor Q24 is coupled to a source terminal of Q23. A second terminal of resistor R24 is coupled to a gate terminal of enhanced mode MOSFET transistor Q25 and to a first terminal of resistor R23. A drain terminal of transistor Q25 is coupled to a second terminal of resistor R23 and to a collector terminal of pnp transistor Q22. The drain of transistor Q23 is coupled to a second terminal of resistor R21, to a collector terminal of pnp transistor Q21, to a base terminal of transistor Q21, and to a base terminal of transistor Q22. The positive voltage terminal T2 of the network power supply is coupled to an emitter terminal of transistor Q21, to an emitter terminal of transistor Q22, and to a second terminal of current source I22. Input signals are applied to a gate terminal of transistor Q27 and to a gate terminal of transistor Q28. The output signal is obtained from the collector terminal of transistor Q22.
As will be clear to those skilled in the art, the stage current dependent on the SIGNAL IN in FIG. 1 can be reduced by increasing the resistor values R11 and R12 to arbitrarily high values. The higher the value of the resistors, the smaller the stage current dependence on the SIGNAL IN. However, the response of the circuit is compromised by this approach. The gate capacitance of transistor Q12 must be charged and discharged through the bias setting resistors, which because of the high values of resistance, limit the dynamic response. A sufficiently fast step alteration in the input signal can induce an unequal voltage distribution in the input circuit which can result in the destruction of the transistors. The present operational amplifier input circuit permits the values of resistance for the bias setting resistors to be sufficiently low to avoid damage to the transistors during dynamic operation while minimizing the variations in stage current.
In the operation of FIG. 2, the circuit prevents excessive voltage from being generated across the differential amplifier. The current through current source I22 established a constant and low voltage across transistors Q27 and Q28. The remaining supply voltage is distributed across the transistor pair Q23 and Q24, the transistor pair Q25 and Q26, and the transistor pair Q29 and Q20. With a zero common mode voltage, the gate terminal of transistor Q28 and the gate terminal Q27 are coupled to ground terminal (i.e., the applied voltage equals zero volts). With the zero common mode voltage, approximately one half of the supply voltage will be developed across the transistor pair Q23 and Q24 in the portion of the circuit coupled in series with transistor Q27 and approximately one half the supply voltage will be developed across the transistor pair Q25 and Q26 in the portion of the circuit coupled in series with the transistor Q28. The remaining half of the supply voltage will be developed across the transistor pair Q29 and Q20. One quarter of the supply voltage will be developed across each transistor of the transistor pairs. As the common mode voltage varies, the voltage developed across each transistor of the transistor pairs will vary. As in the circuit of FIG. 1, the current in the resistance divider networks will change, the change being reflected in the current through the differential amplifier (i.e., transistors Q27 and Q28). Whenever the current through the differential amplifier changes, the offset voltage and the drift characteristics of the input stage will change.
A need has been an input amplifier stage providing an extended input signal to an operational amplifier for which the offset voltage and the drift characteristics will be minimized for changes in the input common mode voltage and power supply voltage.